Table of Contents
Advertisement
Exceptions
5-16
Figure 5-4 on page 5-15 shows the latest point at which INTISR[9] can pre-empt
before the first instruction of the ISR for INTISR[8] enters Fetch stage. The ISR fetch
for INTISR[8] is aborted when INTISR[9] is received, and the processor then initiates
the vector fetch for INTISR[9]. A higher priority interrupt after that point is managed
as pre-emption.
In the cycle that the ISR for INTISR[9] enters execute:
•
ETMINSTAT[2:0] indicates that the ISR has been entered (3'b001). This is a
1-cycle pulse.
•
CURRPRI[7:0] indicates the priority of the active interrupt. CURRPRI remains
asserted throughout the duration of the ISR.
•
ETMINTNUM[8:0] indicates the number of the active interrupt.
ETMINTNUM remains asserted throughout the duration of the ISR.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
ARM DDI 0337G
Unrestricted Access
Advertisement
Table of Contents
