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ARM DDI 0337G
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Note
SWCLKTCK, DBGCLK, and TRACECLKIN only require to be driven if your
implementation contains Serial Wire JTAG Debug Port (SWJ-DP), Serial Wire Debug
Port (SW-DP), and TPIU blocks respectively. Otherwise, the clock inputs must be tied
off.
Note
The processor also contains a STCLK input. This port is not a clock. It is a reference
input for the SysTick counter, and it must be less than half the frequency of FCLK.
STCLK is synchronized internally by the processor to FCLK.
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Clocking and Resets
6-3
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