Pending Register (Exti_Pr); Exti Register Map; Table 47. External Interrupt/Event Controller Register Map And Reset Values - ST STM32F40 Series Reference Manual

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Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 SWIERx: Software Interrupt on line x

Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the

interrupt is enabled on this line on the EXTI_IMR and EXTI_EMR, an interrupt request is

This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).

Pending register (EXTI_PR)

Address offset: 0x14

Reset value: undefined

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 PRx: Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line. This bit is

cleared by writing a 1 to the bit or by changing the sensitivity of the edge detector.

External interrupt/event controller register map and reset values

gives the EXTI register map and the reset values.

Doc ID 018909 Rev 4

Interrupts and events

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