Table 96. Exti Register Map Sections - ST STM32WL55JC Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Extended interrupts and event controller (EXTI)
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 FT22: falling trigger event configuration bit of configurable event input 22
Note: The configurable event inputs are edge triggered. No glitch must be generated on
Bit 21 FT21: falling trigger event configuration bit of configurable event input 21
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 FT16: falling trigger event configuration bit of configurable event input 16
Bit 15 FT15: falling trigger event configuration bit of configurable event input 15
Bit 14 FT14: falling trigger event configuration bit of configurable event input 14
Bit 13 FT13: falling trigger event configuration bit of configurable event input 13
Bit 12 FT12: falling trigger event configuration bit of configurable event input 12
Bit 11 FT11: falling trigger event configuration bit of configurable event input 11
Bit 10 FT10: falling trigger event configuration bit of configurable event input 10
Bit 9 FT9: falling trigger event configuration bit of configurable event input 9
Bit 8 FT8: falling trigger event configuration bit of configurable event input 8
Bit 7 FT7: falling trigger event configuration bit of configurable event input 7
Bit 6 FT6: falling trigger event configuration bit of configurable event input 6
Bit 5 FT5: falling trigger event configuration bit of configurable event input 5
Bit 4 FT4: falling trigger event configuration bit of configurable event input 4
Bit 3 FT3: falling trigger event configuration bit of configurable event input 3
Bit 2 FT2: falling trigger event configuration bit of configurable event input 2
Bit 1 FT1: falling trigger event configuration bit of configurable event input 1
Bit 0 FT0: falling trigger event configuration bit of configurable event input 0
16.6.3
EXTI software interrupt event register (EXTI_SWIER1)
Address offset: 0x008
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
SWI15 SWI14 SWI13 SWI12 SWI11 SWI10
rw
rw
rw
rw
514/1454
0: falling trigger disabled (for event and interrupt) for input line
1: falling trigger enabled (for event and interrupt) for input line
these inputs. If a falling edge on the configurable event input occurs while writing to the
register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this
case, both edges generate a trigger.
27
26
25
Res.
Res.
Res.
11
10
9
SWI9
rw
rw
rw
24
23
22
Res.
Res.
SWI22
SWI21
rw
8
7
6
SWI8
SWI7
SWI6
SWI5
rw
rw
rw
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
rw
5
4
3
2
SWI4
SWI3
SWI2
rw
rw
rw
rw
RM0453
17
16
Res.
SWI16
rw
1
0
SWI1
SWI0
rw
rw

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