Standby Mode; Table 23. Standby Mode Entry And Exit - ST STM32F40 Series Reference Manual

Power controller (PWR)
5.3.5

Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex™-M4F deepsleep mode, with the voltage regulator disabled. The 1.2 V domain is
consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are also
switched off. SRAM and register contents are lost except for registers in the backup domain
(RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see
Figure 7).
Entering Standby mode
Refer to
In Standby mode, the following features can be selected by programming individual control
bits:
●
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 18.3
●
Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR)
●
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
backup domain control register (RCC_BDCR)
Exiting Standby mode
The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG
Reset, a rising edge on WKUP pin, an RTC alarm, a tamper event, or a time stamp event is
detected. All registers are reset after wakeup from Standby except for
control/status register
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the
power control/status register (PWR_CSR)
Refer to
Table 23.
Standby mode
Mode entry
Mode exit
Wakeup latency
101/1422
Table 23 for more details on how to enter Standby mode.
in Section 18: Independent watchdog
(PWR_CSR).
Table 23 for more details on how to exit Standby mode.
Standby mode entry and exit
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP in Cortex™-M4F System Control register
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)
– Clear the RTC flag corresponding to the chosen wakeup source (RTC
Alarm A, RTC Alarm B, RTC wakeup, Tamper or Timestamp flags)
WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time stamp event, external reset in NRST pin, IWDG reset.
Reset phase.
Doc ID 018909 Rev 4
(IWDG).
indicates that the MCU was in Standby mode.
Description
RM0090
PWR power
PWR