Figure 170. Counter Timing Diagram With Prescaler Division Change From 1 To 2; Figure 171. Counter Timing Diagram With Prescaler Division Change From 1 To 4 - ST STM32F101 series Reference Manual

Basic timers (TIM6&TIM7)
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as the TIMx_PSC control register is buffered. The new
prescaler ratio is taken into account at the next update event.
Figure 170
ratio is changed on the fly.

Figure 170. Counter timing diagram with prescaler division change from 1 to 2

Figure 171. Counter timing diagram with prescaler division change from 1 to 4

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and Figure 171 give some examples of the counter behavior when the prescaler
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
DocID13902 Rev 15
F7 F8 F9 FA FB FC 00
0
0
0 0 1
F7 F8 F9 FA FB FC
0
0
0
01 02 03
1
1
0 1 0 1 0 1
00 01
3
3
0 1 2 3 0 1 2 3
RM0008