Af Remap And Debug I/O Configuration Register (Afio_Mapr) - ST STM32F101 series Reference Manual

RM0008
9.4.2

AF remap and debug I/O configuration register (AFIO_MAPR)

Address offset: 0x04
Reset value: 0x0000 0000
Memory map and bit definitions for low-, medium- high- and XL-density
devices:
31 30 29
Reserved
Reserved
15 14 13
PD01_ TIM4_
CAN_REMAP
REMA REMA
[1:0]
P
rw rw rw
Bits 31:27
Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration
Bits 23:21
Bits 20 ADC2_ETRGREG_REMAP: ADC 2 external trigger regular conversion remapping
Bits 19 ADC2_ETRGINJ_REMAP: ADC 2 external trigger injected conversion remapping
Bits 18 ADC1_ETRGREG_REMAP: ADC 1 external trigger regular conversion remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
28 27 26 25
SWJ_
CFG[2:0]
w w
SWJ_CFG[2:0]
w w
12 11 10 9
TIM3_REMAP TIM2_REMAP
[1:0] [1:0]
P
rw rw rw rw
Reserved
These bits are write-only (when read, the value is undefined). They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD
®
access to the Cortex debug port. The default state after reset is SWJ ON without trace.
This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /
JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: no effect
Reserved.
Set and cleared by software. This bit controls the trigger input connected to ADC2 external
trigger regular conversion. When this bit is reset, the ADC2 external trigger regular
conversion is connected to EXTI11. When this bit is set, the ADC2 external event regular
conversion is connected to TIM8_TRGO.
Set and cleared by software. This bit controls the trigger input connected to ADC2 external
trigger injected conversion. When this bit is reset, the ADC2 external trigger injected
conversion is connected to EXTI15. When this bit is set, the ADC2 external event injected
conversion is connected to TIM8_Channel4.
Set and cleared by software. This bit controls the trigger input connected to ADC1
External trigger regular conversion. When reset the ADC1 External trigger regular
conversion is connected to EXTI11. When set the ADC1 External Event regular conversion
is connected to TIM8 TRGO.
24 23 22
Reserved
w
w
8 7 6
TIM1_REMAP
[1:0]
rw rw rw
DocID13902 Rev 15
21 20 19
ADC2_ ADC1_E
ADC2_E
ETRG TRGRE
TRGINJ_
REG_R G_REMA
REMAP
EMAP
rw rw
Reserved
5 4 3
USART2 USART1
USART3_
_
REMAP[1:0]
REMAP REMAP
rw rw rw
18 17 16
ADC1_
TIM5C
ETRGI
H4_IRE
NJ_RE
MAP
P MAP
rw rw rw
TIM5C
H4_IRE
MAP
rw
2 1 0
I2C1_ SPI1_
_ REMA REMA
P P
rw rw rw
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