Figure 266. Audio Sampling Frequency Definition; Figure 267. I - ST STM32F101 series Reference Manual

Serial peripheral interface (SPI)
It will be: I
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
I2SxCLK
1. Where x could be 2 or 3.
Figure 266
system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock). For
connectivity line devices, tThe I2SxCLK source can be either SYSCLK or the PLL3 VCO
(2 × PLL3CLK) clock in order to achieve the maximum accuracy. This selection is made
using the I2S2SRC and I2S3SRC bits in the RCC_CFGR2 register.
The audio sampling frequency can be 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz,
16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
S
When the master clock is disabled (MCKOE bit cleared):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
S
723/1128
2
S bitrate = 32 x 2 x F

Figure 266. Audio sampling frequency definition

16-bit or 32-bit Left channel
sampling point
F : Audio sampling frequency
S

Figure 267. I

8-bit Linear
Divider +
reshaping stage
I2SDIV[7:0]
MCKOE ODD
presents the communication clock architecture. . The I2SxCLK source is the
if the packet length is 32-bit wide.
S
16-bit or 32-bit Right channel
32-bits or 64-bits
F
S
2
S clock generator architecture
Divider by 4
I2SMOD
DocID13902 Rev 15
sampling point
0
0
Div2
1
1
MCKOE
CHLEN
RM0008
MCK
CK