Table 78. Summary Of Dma1 Requests For Each Channel - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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Peripherals Channel 1

DMA2 controller

The 5 requests from the peripherals (TIMx[5,6,7,8], ADC3, SPI/I2S3, UART4,

DAC_Channel[1,2] and SDIO) are simply logically ORed before entering the DMA2, this

means that only one request must be enabled at a time. Refer to

The peripheral DMA requests can be independently activated/de-activated by programming

the DMA control bit in the registers of the corresponding peripheral.

The DMA2 controller and its relative requests are available only in high-density, XL-density

and connectivity line devices.

lists the DMA requests for each channel.

Table 78. Summary of DMA1 requests for each channel

USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX

DocID13902 Rev 15

Direct memory access controller (DMA)

Figure 51: DMA2 request

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