ST STM32F101 series Reference Manual page 281
Advanced arm-based 32-bit mcus
Hide thumbs
Also See for STM32F101 series:
- Reference manual (501 pages) ,
- User manual (14 pages) ,
- Application note (29 pages)
Table of Contents
Advertisement
Direct memory access controller (DMA)
request signals
281/1128
Figure 50. DMA1 request mapping
Peripheral
ADC1
TIM2_CH3
TIM4_CH1
SW trigger (MEM2MEM bit)
USART3_TX
TIM1_CH1
TIM2_UP
TIM3_CH3
SW trigger (MEM2MEM bit)
SPI1_RX
USART3_RX
TIM1_CH2
TIM3_CH4
TIM3_UP
SW trigger (MEM2MEM bit)
SPI1_TX
USART1_TX
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM4_CH2
SW trigger (MEM2MEM bit)
SPI/I2S2_RX
I2C2_TX
USART1_RX
TIM1_UP
SPI/I2S2_TX
TIM2_CH1
SW trigger (MEM2MEM bit)
TIM4_CH3
I2C2_RX
USART2_RX
TIM1_CH3
TIM3_CH1
TIM3_TRIG
SW TRIGGER (MEM2MEM bit)
I2C1_TX
USART2_TX
TIM2_CH2
TIM2_CH4
SW trigger (MEM2MEM bit)
TIM4_UP
I2C1_RX
DocID13902 Rev 15
HW request 1
Channel 1 EN bit
HW request 2
Channel 2 EN bit
HW request 3
Channel 3 EN bit
HW request 4
Channel 4 EN bit
HW request 5
Channel 5 EN bit
HW REQUEST 6
Channel 6 EN bit
HW request 7
Channel 7 EN bit
Fixed hardware priority
High priority
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Low priority
RM0008
internal
DMA1
request
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32F101 series and is the answer not in the manual?
Questions and answers