Table 114. Fsmc_Bcrx Bit Fields; Table 115. Fsmc_Btrx Bit Fields - ST STM32F101 series Reference Manual

Flexible static memory controller (FSMC)
Bit
number
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
515/1128

Table 114. FSMC_BCRx bit fields

Bit name
Reserved
CBURSTRW
Reserved
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
MTYP
MUXEN
MBKEN

Table 115. FSMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x1
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+3 HCLK cycles) for
read accesses.
DATAST
This value cannot be 0 (minimum is 1).
ADDHLD Don't care
Duration of the first access phase (ADDSET+1 HCLK cycles) for
ADDSET
read accesses.
DocID13902 Rev 15
0x000
0x0 (no effect on asynchronous mode)
0x0
Set to 1 if the memory supports this feature. Otherwise keep at
0.
0x1 for mode B, 0x0 for mode 2
0x0 (no effect on asynchronous mode)
As needed
Don't care
0x0
Meaningful only if bit 15 is 1
0x0
0x1
0x1
As needed
0x2 (NOR Flash memory)
0x0
0x1
Value to set
Value to set
RM0008