Rtc Flag Assertion; Figure 180. Rtc Second And Alarm Waveform Example With Pr=0003, Alarm=00004; Figure 181. Rtc Overflow Waveform Example With Pr=0003 - ST STM32F101 series Reference Manual

Real-time clock (RTC)
18.3.5

RTC flag assertion

The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update
of the RTC Counter.
The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the
counter reaches 0x0000.
The RTC_Alarm and RTC Alarm flag (ALRF) (see
Core clock cycle before the counter reaches the RTC Alarm value stored in the Alarm
register increased by one (RTC_ALR + 1). The write operation in the RTC Alarm and RTC
Second flag must be synchronized by using one of the following sequences:
•
Use the RTC Alarm interrupt and inside the RTC interrupt routine, the RTC Alarm
and/or RTC Counter registers are updated.
•
Wait for SECF bit to be set in the RTC Control register. Update the RTC Alarm and/or
the RTC Counter register.

Figure 180. RTC second and alarm waveform example with PR=0003, ALARM=00004

RTCCLK
RTC_PR 0002 0001 0000 0003
RTC_Second
RTC_CNT 0000
RTC_ALARM
ALRF
(not powered
in Standby)

Figure 181. RTC Overflow waveform example with PR=0003

RTCCLK
RTC_PR 0002 0001 0000 0003
RTC_Second
RTC_CNT FFFFFFFB
RTC_Overflow
OWF
(not powered
in Standby)
477/1128
0002 0001 0000 0003 0002 0001
0001 0002
0002 0001 0000 0003 0002 0001
FFFFFFFC FFFFFFFD
DocID13902 Rev 15
Figure 180) are asserted on the last RTC
0000 0003 0002 0001 0000 0003
0003
0000 0003 0002 0001 0000 0003
FFFFFFFE
0002 0001 0000 0003 0002 0001
0004 0005
1 RTCCLK
can be cleared by software
0002 0001 0000 0003 0002 0001
FFFFFFFF 0000
1 RTCCLK
can be cleared by software
RM0008
0000 0003
0000 0003