Pwm Mode; Figure 83. Output Compare Mode, Toggle On Oc1 - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32F101 series:

Table of Contents

PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined

by the value of the TIMx_ARR register and a duty cycle determined by the value of the

TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx

output) by writing '110' (PWM mode 1) or '111' (PWM mode 2) in the OCxM bits in the

TIMx_CCMRx register. You must enable the corresponding preload register by setting the

OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in

upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event

occurs, before starting the counter, you have to initialize all the registers by setting the UG

bit in the TIMx_EGR register.

OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It

can be programmed as active high or active low. OCx output is enabled by a combination of

the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).

Refer to the TIMx_CCER register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine

whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction

of the counter).

The timer is able to generate PWM in edge-aligned mode or center-aligned mode

depending on the CMS bits in the TIMx_CR1 register.

Write B201h in the CC1R register

DocID13902 Rev 15

Advanced-control timers (TIM1&TIM8)

Match detected on CCR1

Interrupt generated if enabled

Do you have a question about the STM32F101 series and is the answer not in the manual?