Capture/Compare Channels; Figure 158. Control Circuit In External Clock Mode 1; Figure 159. Capture/Compare Channel (Example: Channel 1 Input Stage) - ST STM32F101 series Reference Manual

General-purpose timers (TIM9 to TIM14)
16.3.4

Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 159
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 159. Capture/compare channel (example: channel 1 input stage)

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
427/1128

Figure 158. Control circuit in external clock mode 1

CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
to Figure 161 give an overview of one capture/compare channel.
TI1
TI1F
filter
f downcounter
DTS
ICF[3:0]
TIMx_CCMR1
DocID13902 Rev 15
TI2
34
TIF
Write TIF=0
TI1F_Rising
0
TI1FP1
Edge
Detector
TI1F_Falling
1
CC1P/CC1NP
TIMx_CCER
TI2F_rising
0
(from channel 2)
TI2F_falling
1
(from channel 2)
35 36
TI1F_ED
to the slave mode controller
01
TI2FP1
IC1
divider
10
/1, /2, /4, /8
TRC
11
(from slave mode
controller)
CC1S[1:0] ICPS[1:0]
TIMx_CCMR1
RM0008
IC1PS
CC1E
TIMx_CCER