Figure 22. Single Adc Block Diagram - ST STM32F101 series Reference Manual

RM0008
ADCx_IN0
ADCx_IN1
ADCx_IN15
EXTI_15
EXTI_11
1. ADC3 has regular and injected conversion triggers different from those of ADC1 and ADC2.
2. TIM8_CH4 and TIM8_TRGO with their corresponding remap bits exist only in High-density and XL-density
products.

Figure 22. Single ADC block diagram

End of conversion
End of injected conversion
Analog watchdog event
V
REF+
V
REF-
V
DDA
V
SSA
Analog
MUX
GPIO
up to 4
Ports
up to 16
Temp. sensor
V
REFINT
JEXTSEL[2:0] bits
TIM1_TRGO
TIM1_CH4
TIM2_TRGO
TIM2_CH1
TIM3_CH4
TIM4_TRGO
(2)
TIM8_CH4
ADCx-ETRGINJ_REMAP bit
EXTSEL[2:0] bits
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM2_CH2
TIM3_TRGO
TIM4_CH4
(2)
TIM8_TRGO
ADCx_ETRGREG_REMAP bit
DocID13902 Rev 15
Interrupt
Flags
enable bits
EOCIE
EOC
JEOC
JEOCIE
AWD AWDIE
Compare Result
High Threshold (12 bits)
Low Threshold (12 bits)
Injected data registers
Injected
channels
Regular
channels
JEXTRIG
bit
Start trigger
(injected group)
EXTRIG
bit
Start trigger
(regular group)
Analog-to-digital converter (ADC)
ADC Interrupt to NVIC
Analog watchdog
(4 x 16 bits)
Regular data register
(16 bits)
DMA request
ADCCLK
Analog to digital
converter
From ADC prescaler
JEXTSEL[2:0] bits
TIM1_TRGO
TIM1_CH4
TIM4_CH3
TIM8_CH2
TIM8_CH4
TIM5_TRGO
TIM5_CH4
EXTSEL[2:0] bits
TIM3_CH1
TIM2_CH3
TIM1_CH3
TIM8_CH1
TIM8_TRGO
TIM5_CH1
TIM5_CH3
Triggers for ADC3
JEXTRIG
bit
Start trigger
(injected group)
EXTRIG
bit
Start trigger
(regular group)
(1)
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