Nand Flash/Pc Card Control Registers - ST STM32F101 series Reference Manual

Flexible static memory controller (FSMC)
xxWAITx >= 4 + max_wait_assertion_time/HCLK
Where max_wait_assertion_time is the maximum time taken by NWAIT to go low once
nOE/nWE or nIORD/nIOWR is low.
After the de-assertion of nWAIT, the FSMC extends the WAIT phase for 4 HCLK clock
cycles.
21.6.8

NAND Flash/PC Card control registers

The NAND Flash/PC Card control registers have to be accessed by words (32 bits).
PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4)
Address offset: 0xA0000000 + 0x40 + 0x20 * (x – 1), x = 2..4
Reset value: 0x0000 0018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:20
Bits 19:17 ECCPS: ECC page size.
Bits 16:13 TAR: ALE to RE delay.
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 12:9 TCLR: CLE to RE delay.
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7
Bit 6 ECCEN: ECC computation logic enable bit
547/1128
ECCPS
rw rw rw rw rw rw rw rw rw rw rw
Reserved, must be kept at reset value.
Defines the page size for the extended ECC:
000: 256 bytes
001: 512 bytes
010: 1024 bytes
011: 2048 bytes
100: 4096 bytes
101: 8192 bytes
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Time is: t_ar = (TAR + SET + 4) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 4) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Reserved, must be kept at reset value.
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
TAR
DocID13902 Rev 15
9 8 7 6 5
TCLR PWID
Res.
rw rw rw rw rw rw
RM0008
4 3 2 1 0