Figure 8. Clock Tree - ST STM32F101 series Reference Manual

Low-, medium-, high- and XL-density reset and clock control (RCC)
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For full details about the internal and external clock source characteristics, please refer to the "Electrical
characteristics" section in your device datasheet.
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is
36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2
The RCC feeds the Cortex
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex
(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by
the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.
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Figure 8. Clock tree

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System Timer (SysTick) external clock with the AHB clock
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clock