Figure 278. Usart Block Diagram - ST STM32F101 series Reference Manual

RM0008
TX
IrDA
SIR
RX
ENDEC
BLOCK
SW_RX
nRTS
Hardware
flow
nCTS
controller
USARTDIV = DIV_Mantissa + (DIV_Fraction / 16)
Universal synchronous asynchronous receiver transmitter (USART)

Figure 278. USART block diagram

PWDATA
Write
(CPU or DMA)
Transmit Data Register (TDR)
Transmit Shift Register
CR3
DMAT
DMAR SCEN NACK
CR2
USART Address
TRANSMIT
CONTROL
CR1
RXNE IDLE
TXEIE TCIE TE
IE
IE
USART
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
/16
f
PCLKx(x=1,2)
DocID13902 Rev 15
Read
(CPU or DMA)
Receive Data Register (RDR)
Receive Shift Register
GTPR
GT PSC
CR2
HD IRLP
IREN
LINE
M
UE
WAKE
UP
UNIT
CTS LBD
RE RWU SBK
USART_BRR
TRANSMITTER RATE
TE
CONTROL
/
USARTDIV
DIV_Mantissa
15
RECEIVER RATE
RE CONTROL
CONVENTIONAL BAUD RATE GENERATOR
PRDATA
(DATA REGISTER) DR
CK CONTROL
STOP[1:0] CKEN CPOL CPHA LBCL
CR1
WAKE PCE PS PEIE
RECEIVER
CLOCK
RECEIVER
CONTROL
SR
TXE TC RXNE IDLE ORE NE FE
DIV_Fraction
4 0
CK
PE
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