Debug Mode; Tim6&Tim7 Registers; Tim6&Tim7 Control Register 1 (Timx_Cr1); Figure 178. Control Circuit In Normal Mode, Internal Clock Divided By 1 - ST STM32F101 series Reference Manual

Basic timers (TIM6&TIM7)

Figure 178. Control circuit in normal mode, internal clock divided by 1

Counter clock = CK_CNT = CK_PSC
17.3.4

Debug mode

When the microcontroller enters the debug mode (Cortex
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to
support for timers, watchdog, bxCAN and
17.4 TIM6&TIM7 registers
Refer to
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
17.4.1 TIM6&TIM7 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 ARPE: Auto-reload preload enable
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
467/1128
CK_INT
CEN=CNT_EN
CNT_INIT
Counter register
Section 2.1 on page 47
12 11 10 9
Reserved
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
UG
31 32 33 34 35 36
I2C.
for a list of abbreviations used in register descriptions.
8 7 6
ARPE
Reserved
rw
DocID13902 Rev 15
00 01 02 03 04 05 06 07
®
-M3 core - halted), the TIMx
Section 31.16.2: Debug
5 4 3 2
OPM URS
rw rw
RM0008
1 0
UDIS CEN
rw rw