General-Purpose I/O (Gpio); Atomic Bit Set Or Reset; Table 20. Port Bit Configuration Table; Table 21. Output Mode Bits - ST STM32F101 series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Configuration mode
General purpose
output
Alternate Function
output
Input
9.1.1

General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and the I/O ports are
configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b).
The JTAG pins are in input PU/PD after reset:
PA15: JTDI in PU
PA14: JTCK in PD
PA13: JTMS in PU
PB4: NJTRST in PU
When configured as output, the value written to the Output Data register (GPIOx_ODR) is
output on the I/O pin. It is possible to use the output driver in Push-Pull mode or Open-Drain
mode (only the N-MOS is activated when outputting 0).
The Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every
APB2 clock cycle.
All GPIO pins have an internal weak pull-up and weak pull-down which can be activated or
not when configured as input.
9.1.2

Atomic bit set or reset

There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify only one or several bits in a single atomic APB2 write
access. This is achieved by programming to '1' the Bit Set/Reset Register (GPIOx_BSRR,
161/1128

Table 20. Port bit configuration table

Push-pull
Open-drain
Push-pull
Open-drain
Analog
Input floating
Input pull-down
Input pull-up

Table 21. Output MODE bits

MODE[1:0]
00
01
10
11
DocID13902 Rev 15
CNF1 CNF0 MODE1
0
0
1
0
1
see
1
0
0
1
1 0
Meaning
Reserved
Max. output speed 10 MHz
Max. output speed 2 MHz
Max. output speed 50 MHz
RM0008
PxODR
MODE0
register
0 or 1
01
0 or 1
10
11
don't care
Table 21
don't care
don't care
don't care
00
0
1