Table 79. Summary Of Dma2 Requests For Each Channel; Figure 51. Dma2 Request Mapping - ST STM32F101 series Reference Manual

Direct memory access controller (DMA)
Peripheral request signals
TIM6_UP/DAC_Channel1
TIM7_UP/DAC_Channel2
Table 79
Peripherals
ADC3
SPI/I2S3
UART4
SDIO
TIM5
TIM6/
DAC_Channel1
TIM7
TIM8
283/1128

Figure 51. DMA2 request mapping

TIM5_CH4
TIM5_TRIG
TIM8_CH3
TIM8_UP
SW trigger (MEM2MEM bit)
SPI/I2S3_RX
TIM8_CH4
TIM8_TRIG
TIM8_COM
TIM5_CH3
SW trigger (MEM2MEM bit)
TIM5_UP
SPI/I2S3_TX
TIM8_CH1
UART4_RX
SW trigger (MEM2MEM bit)
TIM5_CH2
SDIO
SW trigger (MEM2MEM bit)
ADC3
TIM8_CH2
TIM5_CH1
SW trigger (MEM2MEM bit)
UART4_TX
lists the DMA2 requests for each channel.

Table 79. Summary of DMA2 requests for each channel

Channel 1
(1)
SPI/I2S3_RX
(1)
TIM5_CH4
TIM5_TRIG
TIM8_CH3
TIM8_UP
DocID13902 Rev 15
HW request 1
Channel 1 EN bit
HW request 2
Channel 2 EN bit
HW request 3
Channel 3 EN bit
HW request 4
Channel 4 EN bit
HW request 5
Channel 5 EN bit
Channel 2 Channel 3
SPI/I2S3_TX
UART4_RX
TIM5_CH3
TIM5_UP
TIM6_UP/
DAC_Channel
1
TIM8_CH4
TIM8_TRIG TIM8_CH1
TIM8_COM
Fixed hardware priority
HIGH PRIORITY
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
LOW PRIORITY
Channel 4 Channel 5
UART4_TX
SDIO
TIM5_CH2 TIM5_CH1
TIM7_UP/
DAC_Channel
2
TIM8_CH2
RM0008
internal
DMA2
request
ADC3