ST STM32F101 series Reference Manual page 343

Advanced-control timers (TIM1&TIM8)
Bit 6 TG: Trigger generation
Bit 5 COMG: Capture/Compare control update generation
Note: This bit acts only on channels having a complementary output.
Bit 4 CC4G: Capture/Compare 4 generation
Bit 3 CC3G: Capture/Compare 3 generation
Bit 2 CC2G: Capture/Compare 2 generation
Bit 1 CC1G: Capture/Compare 1 generation
Bit 0 UG: Update generation
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This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
This bit can be set by software, it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits
refer to CC1G description
refer to CC1G description
refer to CC1G description
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).
DocID13902 Rev 15
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