Tim10/11/13/14 Status Register (Timx_Sr); Tim10/11/13/14 Event Generation Register (Timx_Egr) - ST STM32F101 series Reference Manual
Advanced arm-based 32-bit mcus
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Also See for STM32F101 series:
- Reference manual (501 pages) ,
- User manual (14 pages) ,
- Application note (29 pages)
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General-purpose timers (TIM9 to TIM14)
16.5.2
TIM10/11/13/14 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
13
Reserved
Bits 15:10
Reserved, must be kept at reset value.
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:2
Reserved, must be kept at reset value.
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value. It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
on IC1 which matches the selected polarity).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
16.5.3
TIM10/11/13/14 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15
14
13
453/1128
12
11
10
9
CC1OF
rc_w0
–
At overflow and if UDIS='0' in the TIMx_CR1 register.
–
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS='0' and UDIS='0' in the TIMx_CR1 register.
12
11
10
9
Reserved
DocID13902 Rev 15
8
7
6
5
Reserved
8
7
6
5
RM0008
4
3
2
1
CC1IF
rc_w0
4
3
2
1
CC1G
w
0
UIF
rc_w0
0
UG
w
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