Table 116. Fsmc_Bwtrx Bit Fields; Figure 194. Mode C Read Accesses - ST STM32F101 series Reference Manual

RM0008
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Note: The FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its
content is don't care.
Mode C - NOR Flash - OE toggling

Table 116. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x1
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST+3 HCLK cycles for write accesses).
DATAST
This value cannot be 0 (minimum is 1).
ADDHLD Don't care
Duration of the first access phase (ADDSET+1 HCLK cycles) for
ADDSET
write accesses.

Figure 194. Mode C read accesses

A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
(ADDSET +1)
HCLK cycles
DocID13902 Rev 15
Flexible static memory controller (FSMC)
Value to set
Memory transaction
data driven
by memory
(DATAST + 1)
HCLK cycles
Data sampled
2 HCLK
cycles
Data strobe
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