Figure 67. Counter Timing Diagram, Internal Clock Divided By 2; Figure 68. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 69. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F101 series Reference Manual

Advanced-control timers (TIM1&TIM8)

Figure 68. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
303/1128

Figure 67. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 69. Counter timing diagram, internal clock divided by N

CK_PSC
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
DocID13902 Rev 15
0003 0002 0001 0000 0001 0002 0003
0034 0035
20 1F 01
RM0008
0036 0035
00