Mii/Rmii Selection; Figure 333. Rmii Clock Sources; Figure 334. Clock Scheme - ST STM32F101 series Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
RMII clock sources
As described in the
provide this 50 MHz clock signal on its MCO output pin and you then have to configure this
output value through PLL configuration.
29.4.4

MII/RMII selection

The mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the
AFIO_MAPR register. The application has to set the MII/RMII mode while the Ethernet
controller is under reset or before enabling the clocks.
MII/RMII internal clock scheme
The clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s
operations is described in
MII_TX_CLK as AF
(25 MHz or 2.5 MHz)
MII_RX_CLK as AF
(25 MHz or 2.5 MHz)
RMII_REF_CK as AF
(50 MHz)
1. The MII/RMII selection is controlled through bit 23, MII_RMII_SEL, in the AFIO_MAPR register.
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RMII clock sources

Figure 333. RMII clock sources

STM32
25 MHz
PLL
MCO
Figure

Figure 334. Clock scheme

GPIO and AF
controller
50 MHz
GPIO and AF
controller
DocID13902 Rev 15
section, the STM32F10xxxSTM32F107xx could
REF_CLK
50 MHz
50 MHz
334.
25 MHz or 2.5 MHz
0
1
0 MII
Sync. divider
1 RMII
/2 for 100 Mb/s
/20 for 10 Mb/s
0
25 MHz or 2.5 MHz
1
External
PHY
For 10/100 Mbit/s
25 MHz MACTXCLK
or 2.5 MHz
(1)
25 MHz
MACRXCLK
or 2.5 MHz
HCLK
HCLK
must be greater
than 25 MHz
RM0008
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MAC
TX
AHB
RX
RMII
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