ST STM32F101 series Reference Manual page 417

General-purpose timers (TIM2 to TIM5)
Offset Register
TIMx_ARR
0x2C
Reset value
0x30
TIMx_CCR1
0x34
Reset value
TIMx_CCR2
0x38
Reset value
TIMx_CCR3
0x3C
Reset value
TIMx_CCR4
0x40
Reset value
0x44
TIMx_DCR
0x48
Reset value
TIMx_DMAR
0x4C
Reset value
Refer to
417/1128
Table 88. TIMx register map and reset values (continued)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 3 on page 51 for the register boundary addresses.
0
Reserved
0
0
0
0
Reserved
0
DocID13902 Rev 15
ARR[15:0]
0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0
RM0008
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0 0 0