ST STM32F101 series Reference Manual page 762
Advanced arm-based 32-bit mcus
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Also See for STM32F101 series:
- Reference manual (501 pages) ,
- User manual (14 pages) ,
- Application note (29 pages)
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RM0008
1.
Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved
to this address from the memory after each TxE event.
2.
Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register
in the case of a bouble buffer mode). The data will be loaded into I2C_DR from this
memory after each TxE event.
3.
Configure the total number of bytes to be transferred in the DMA_SxNDTR register.
After each TxE event, this value will be decremented.
4.
Configure the DMA stream priority using the PL[0:1] bits in the DMA_SxCR register
5.
Set the DIR bit in the DMA_SxCR register and configure interrupts after half transfer or
full transfer depending on application requirements.
6.
Activate the stream by setting the EN bit in the DMA_SxCR register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
2
I
C interface and the DMA generates an interrupt, if enabled, on the DMA stream interrupt
vector.
Note:
Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.
Reception using DMA
DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register.
Data will be loaded from the I2C_DR register to a Memory area configured using the DMA
peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA
stream x for I
1.
Set the I2C_DR register address in DMA_SxPAR register. The data will be moved from
this address to the memory after each RxNE event.
2.
Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register
in the case of a bouble buffer mode). The data will be loaded from the I2C_DR register
to this memory area after each RxNE event.
3.
Configure the total number of bytes to be transferred in the DMA_SxNDTR register.
After each RxNE event, this value will be decremented.
4.
Configure the stream priority using the PL[0:1] bits in the DMA_SxCR register
5.
Reset the DIR bit and configure interrupts in the DMA_SxCR register after half transfer
or full transfer depending on application requirements.
6.
Activate the stream by setting the EN bit in the DMA_SxCR register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
2
I
C interface and DMA generates an interrupt, if enabled, on the DMA stream interrupt
vector.
Note:
Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.
2
C reception (where x is the stream number), perform the following sequence:
DocID13902 Rev 15
Inter-integrated circuit (I
2
C) interface
762/1128
777
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