Data Alignment; Figure 26. Calibration Timing Diagram; Figure 27. Right Alignment Of Data; Figure 28. Left Alignment Of Data - ST STM32F101 series Reference Manual

Analog-to-digital converter (ADC)
(digital word) is calculated for each capacitor, and during all subsequent conversions, the
error contribution of each capacitor is removed using this code.
Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is
over, the CAL bit is reset by hardware and normal conversion can be performed. It is
recommended to calibrate the ADC once at power-on. The calibration codes are stored in
the ADC_DR as soon as the calibration phase ends.
Note: It is recommended to perform a calibration after each power-up.
Before starting a calibration, the ADC must have been in power-on state (ADON bit = '1') for
at least two ADC clock cycles.
CLK
CAL
ADC
Conversion
11.5

Data alignment

ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion.
Data can be left or right aligned as shown in
The injected group channels converted data value is decreased by the user-defined offset
written in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit is
the extended sign value.
For regular group channels no offset is subtracted so only twelve bits are significant.
Injected group
SEXT
Regular group
0
Injected group
SEXT
Regular group
D11
223/1128

Figure 26. Calibration timing diagram

Calibration ongoing
t
CAL

Figure 27. Right alignment of data

SEXT SEXT SEXT D11
0 0 0 D11

Figure 28. Left alignment of data

D11 D10 D9 D8
D10 D9 D8 D7
Calibration Reset by Hardware
Figure 27.
D10 D9 D8 D7
D10 D9 D8 D7
D7 D6 D5 D4
D6 D5 D4 D3
DocID13902 Rev 15
Normal ADC Conversion
and Figure 28.
D6 D5 D4 D3 D2
D6 D5 D4 D3 D2
D3 D2 D1 D0
D2 D1 D0 0
RM0008
D1 D0
D1 D0
0 0 0
0 0 0