Figure 270. Transfer Sequence Diagram For Slave Transmitter - ST STM32F101 series Reference Manual

RM0008
7-bit slave transmitter
S Address
10-bit slave transmitter
S Header
Legend: S= Start, S
EVx= Event (with interrupt if ITEVFEN=1)
EV1: ADDR=1, cleared by reading SR1 followed by reading SR2
EV3-1: TxE=1, shift register empty, data register empty, write Data1 in DR.
EV3: TxE=1, shift register not empty, data register empty, cleared by writing DR
EV3-2: AF=1; AF is cleared by writing '0' in AF bit of SR1 register.
2.
Slave receiver
Following the address reception and after clearing ADDR, the slave receives bytes from the
SDA line into the DR register via the internal shift register. After each byte the interface
generates in sequence:
•
An acknowledge pulse if the ACK bit is set
•
The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bit is set.
If RxNE is set and the data in the DR register is not read before the end of the next data
reception, the BTF bit is set and the interface waits until BTF is cleared by a read from
I2C_SR1 followed by a read from the I2C_DR register, stretching SCL low (see
Transfer sequencing).

Figure 270. Transfer sequence diagram for slave transmitter

A Data1
EV1 EV3-1 EV3
A Address A
EV1
S Header A
r
= Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,
r
DocID13902 Rev 15
Inter-integrated circuit (I
A Data2 A
EV3 EV3
Data1
EV1 EV3_1 EV3
2
C) interface
DataN NA P
.....
EV3-2
A .... DataN NA P
EV3
Figure 271
EV3-2
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