Single-Wire Half-Duplex Communication; Figure 290. Usart Data Clock Timing Diagram (M=1); Figure 291. Rx Data Setup/Hold Time - ST STM32F101 series Reference Manual

RM0008
CK (capture strobe on CK
rising edge in this example)
t
SETUP
Note: The function of CK is different in Smartcard mode. Refer to the Smartcard mode chapter for
more details.
27.3.10

Single-wire half-duplex communication

The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
•
LINEN and CLKEN bits in the USART_CR2 register,
•
SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a single-wire half-duplex protocol. In single-wire
half-duplex mode, the TX and RX pins are connected internally. The selection between half-
and full-duplex communication is made with a control bit 'HALF DUPLEX SEL' (HDSEL in
USART_CR3).
As soon as HDSEL is written to 1:
• RX is no longer used,
•
TX is always released when no data is transmitted. Thus, it acts as a standard IO in idle
or in reception. It means that the IO must be configured so that TX is configured as
floating input (or output high open-drain) when not driven by the USART.
Universal synchronous asynchronous receiver transmitter (USART)

Figure 290. USART data clock timing diagram (M=1)

Idle or preceding
Start
transmission
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Data on TX
(from master)
Start
Data on RX
(from slave)
Capture Strobe

Figure 291. RX data setup/hold time

Data on RX
(from slave)
= 1/16 bit time
t
HOLD
M=1 (9 data bits)
0 1 2 3
LSB
0 1 2 3
LSB
valid DATA bit
t
SETUP
DocID13902 Rev 15
Stop
*
*
*
*
8
4 5 6 7
MSB Stop
4 5 6 7 8
MSB
*
* LBCL bit controls last data clock pulse
t
HOLD
Idle or next
transmission
800/1128
820