Table 127. Fsmc_Bcrx Bit Fields; Figure 203. Synchronous Multiplexed Write Mode - Psram (Cram) - ST STM32F101 series Reference Manual

RM0008

Figure 203. Synchronous multiplexed write mode - PSRAM (CRAM)

1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. NWAIT polarity is set to 0.
3. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Bit No.
31-20
19
18-16
15
14
13
12
11
10

Table 127. FSMC_BCRx bit fields

Bit name
Reserved 0x000
CBURSTRW 0x1
Reserved 0x0
ASCYCWAIT 0x0
EXTMOD 0x0
WAITEN Set to 1 if the memory supports this feature, otherwise keep at 0.
WREN 0x1
WAITCFG 0x0
WRAPMOD 0x0
DocID13902 Rev 15
Flexible static memory controller (FSMC)
Value to set
530/1128
555