Clock Configuration Register (Rcc_Cfgr) - ST STM32F101 series Reference Manual

RM0008
Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
Bit 2
Bit 1 HSIRDY: Internal high-speed clock ready flag
Bit 0 HSION: Internal high-speed clock enable
8.3.2

Clock configuration register (RCC_CFGR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during a clock source switch.
31 30 29
Reserved
15 14 13
ADC PRE[1:0] PPRE2[2:0]
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These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the internal HSI RC.
The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8
MHz ± 1%. The trimming step (F
steps.
Reserved, must be kept at reset value.
Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit
is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.
0: Internal 8 MHz RC oscillator not ready
1: Internal 8 MHz RC oscillator ready
Set and cleared by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby
mode or in case of failure of the external 3-25 MHz oscillator used directly or indirectly as
system clock. This bit can not be cleared if the internal 8 MHz RC is used directly or
indirectly as system clock or is selected to become the system clock.
0: Internal 8 MHz RC oscillator OFF
1: Internal 8 MHz RC oscillator ON
28 27 26 25
MCO[3:0]
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12 11 10 9
PPRE1[2:0]
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DocID13902 Rev 15
Connectivity line devices: reset and clock control (RCC)
) is around 40 kHz between two consecutive HSICAL
hsitrim
24 23 22
OTGFS
PRE
Res.
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8 7 6
HPRE[3:0]
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21 20 19 18
PLLMUL[3:0]
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5 4 3 2
SWS[1:0]
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17 16
PLL PLL
XTPRE SRC
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1 0
SW[1:0]
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