Pll; Lse Clock; Lsi Clock - ST STM32F101 series Reference Manual

RM0008
7.2.3

PLL

The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock
frequency. Refer to
The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL
input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL
enabled, these parameters cannot be changed.
An interrupt can be generated when the PLL is ready if enabled in the
register (RCC_CIR).
If the USB interface is used in the application, the PLL must be programmed to output 48 or
72 MHz. This is needed to provide a 48 MHz USBCLK.
7.2.4

LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in
register (RCC_BDCR).
The LSERDY flag in the
crystal is stable or not. At startup, the LSE crystal output clock signal is not released until
this bit is set by hardware. An interrupt can be generated if enabled in the
register (RCC_CIR).
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the
control register
~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left
Hi-Z. See
7.2.5

LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to
the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
(RCC_CSR).
The LSIRDY flag in the
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the
(RCC_CIR).
Note: LSI calibration is only available on high-density, XL-density and connectivity line devices.
Low-, medium-, high- and XL-density reset and clock control (RCC)
Figure 8 and
Backup domain control register (RCC_BDCR)
(RCC_BDCR). The external clock signal (square, sinus or triangle) with
Figure 9.
Control/status register (RCC_CSR)
DocID13902 Rev 15
Clock control register (RCC_CR).
Clock interrupt
Backup domain control
indicates if the LSE
Clock interrupt
Backup domain
Control/status register
indicates if the low-speed
Clock interrupt register
96/1128
122