ST STM32F101 series Reference Manual page 52

RM0008
Boundary address
0x4001 5800 - 0x4001 7FFF
0x4001 5400 - 0x4001 57FF
0x4001 5000 - 0x4001 53FF
0x4001 4C00 - 0x4001 4FFF
0x4001 4000 - 0x4001 4BFF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2800 - 0x4001 2BFF
0x4001 2400 - 0x4001 27FF
0x4001 2000 - 0x4001 23FF
0x4001 1C00 - 0x4001 1FFF
0x4001 1800 - 0x4001 1BFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0C00 - 0x4001 0FFF
0x4001 0800 - 0x4001 0BFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
Table 3. Register boundary addresses (continued)
Peripheral
Reserved
TIM11 timer
TIM10 timer
TIM9 timer
Reserved
ADC3
USART1
TIM8 timer
SPI1
TIM1 timer
ADC2
ADC1
GPIO Port G
GPIO Port F
GPIO Port E
GPIO Port D
GPIO Port C
GPIO Port B
GPIO Port A
EXTI
AFIO
DocID13902 Rev 15
Memory and bus architecture
Bus Register map
Section 16.5.10 on page 459
Section 16.5.10 on page 459
Section 16.4.13 on page 449
Section 11.12.15 on page 251
Section 27.6.8 on page 820
Section 14.4.21 on page 358
Section 25.5 on page 733
Section 14.4.21 on page 358
APB2 Section 11.12.15 on page 251
Section 11.12.15 on page 251
Section 9.5 on page 194
Section 9.5 on page 194
Section 9.5 on page 194
Section 9.5 on page 194
Section 9.5 on page 194
Section 9.5 on page 194
Section 9.5 on page 194
Section 10.3.7 on page 213
Section 9.5 on page 194
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