Debug Mode; Table 98. Min-Max Timeout Value @36 Mhz (F Pclk1 ) - ST STM32F101 series Reference Manual

RM0008
Prescaler
1
2
4
8
20.5

Debug mode

When the microcontroller enters debug mode (Cortex
either continues to work normally or stops, depending on DBG_WWDG_STOP
configuration bit in DBG module. For more details, refer to
for timers, watchdog, bxCAN and
Table 98. Min-max timeout value @36 MHz (f
WDGTB Min timeout value
0
1
2
3
I2C.
DocID13902 Rev 15
Window watchdog (WWDG)
113 µs
227 µs
455 µs
910 µs
®
-M3 core halted), the WWDG counter
Section 31.16.2: Debug support
)
PCLK1
Max timeout value
7.28 ms
14.56 ms
29.12 ms
58.25 ms
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