Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr) - ST STM32F101 series Reference Manual

Low-, medium-, high- and XL-density reset and clock control (RCC)
7.3.8

APB1 peripheral clock enable register (RCC_APB1ENR)

Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
31 30 29 28
DAC PWR
EN EN
Reserved
rw rw
15 14 13 12
SPI3 SPI2
EN EN
Reserved
rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACEN: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Bit 27 BKPEN: Backup interface clock enable
Bit 26 Reserved, must be kept at reset value.
Bit 25 CANEN: CAN clock enable
Bit 24 Reserved, always read as 0.
Bit 23 USBEN: USB clock enable
115/1128
27 26 25
BKP CAN
EN EN
Res.
rw rw
11 10 9
WWD
GEN
Reserved
rw
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Set and cleared by software.
0: Backup interface clock disabled
1: Backup interface clock enabled
Set and cleared by software.
0: CAN clock disabled
1: CAN clock enabled
Set and cleared by software.
0: USB clock disabled
1: USB clock enabled
DocID13902 Rev 15
24 23 22 21
USB I2C2 I2C1
EN EN EN
Res.
rw rw rw
8 7 6 5
TIM14 TIM13 TIM12 TIM7
EN EN EN EN
rw rw rw rw
20 19 18
UART5E UART4E USART3
N N EN
rw rw rw
4 3 2
TIM6 TIM5 TIM4
EN EN EN
rw rw rw
RM0008
17 16
USART2
EN
Res.
rw
1 0
TIM3 TIM2
EN EN
rw rw