Nor/Psram Control Registers - ST STM32F101 series Reference Manual

RM0008
21.5.6

NOR/PSRAM control registers

The NOR/PSRAM control registers have to be accessed by words (32 bits).
SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4)
Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4
Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4
This register contains the control information of each memory bank, used for SRAMs,
PSRAM and NOR Flash memories.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Bits 31: 20
Bit 19 CBURSTRW: Write burst enable.
Bits 18: 16
Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers
Bit 14 EXTMOD: Extended mode enable.
Reserved
rw
Reserved, must be kept at reset value.
For Cellular RAM (PSRAM) memories, this bit enables the synchronous burst protocol
during write operations. The enable bit for synchronous read accesses is the
BURSTEN bit in the FSMC_BCRx register.
0: Write operations are always performed in asynchronous mode
1: Write operations are performed in synchronous mode.
Reserved, must be kept at reset value.
This bit enables/disables the FSMC to use the wait signal even during an asynchronous
protocol.
0: NWAIT signal is not taken into account when running an asynchronous protocol
(default after reset)
1: NWAIT signal is taken into account when running an asynchronous protocol
This bit enables the FSMC to program the write timings for asynchronous accesses
inside the FSMC_BWTR register, thus resulting in different timings for read and write
operations.
0: values inside FSMC_BWTR register are not taken into account (default after reset)
1: values inside FSMC_BWTR register are taken into account
Note: When the extended mode is disabled, the FSMC can operate in Mode1 or Mode2
as follows:
– Mode 1 is the default mode when the SRAM/PSRAM memory type is selected
(MTYP =0x0 or 0x01)
– Mode 2 is the default mode when the NOR memory type is selected (MTYP =
0x10).
DocID13902 Rev 15
Flexible static memory controller (FSMC)
15 14 13 12 11 10 9
rw rw rw rw rw rw rw rw
8 7 6 5 4 3 2
rw rw rw rw rw rw rw
532/1128
1 0
555