Dac Software Trigger Register (Dac_Swtrigr) - ST STM32F101 series Reference Manual

Digital-to-analog converter (DAC)
Bit 2 TEN1: DAC channel1 trigger enable
This bit set and cleared by software to enable/disable DAC channel1 trigger
0: DAC channel1 trigger disabled and data written into DAC_DHRx register is transferred
one APB1 clock cycle later to the DAC_DOR1 register.
1: DAC channel1 trigger enabled and data transfer from DAC_DHRx register is transferred
three APB1 clock cycles later to the DAC_DOR1 register.
Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to
Bit 1 BOFF1: DAC channel1 output buffer disable
This bit set and cleared by software to enable/disable DAC channel1 output buffer.
0: DAC channel1 output buffer enabled
1: DAC channel1 output buffer disabled
Bit 0 EN1: DAC channel1 enable
This bit set and cleared by software to enable/disable DAC channel1.
0: DAC channel1 disabled
1: DAC channel1 enabled
12.5.2

DAC software trigger register (DAC_SWTRIGR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:2 Reserved.
Bit 1 SWTRIG2: DAC channel2 software trigger
Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR2
Bit 0 SWTRIG1: DAC channel1 software trigger
Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR1
267/1128
DAC_DOR1 register transfer.
27 26 25
11 10 9
Reserved
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
register value is loaded to the DAC_DOR2 register.
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
register value is loaded to the DAC_DOR1 register.
DocID13902 Rev 15
24 23 22 21
Reserved
8 7 6 5
20 19 18 17
4 3 2 1
SWTRI
G2
w
RM0008
16
0
SWTRI
G1
w