Supported Audio Protocols - ST STM32F101 series Reference Manual

Serial peripheral interface (SPI)
The SPI could function as an audio I
setting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same
pins, flags and interrupts as the SPI.
2
The I S shares three common pins with the SPI:
•
SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-
multiplexed data channels (in half-duplex mode only).
• WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
•
CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
An additional pin could be used when a master clock output is needed for some external
audio devices:
•
MCK: Master Clock (mapped separately) is used, when the I
mode (and when the MCKOE bit in the SPI_I2SPR register is set), to output this
additional clock generated at a preconfigured frequency rate equal to 256 × F
F is the audio sampling frequency.
S
2
The I S uses its own clock generator to produce the communication clock when it is set in
master mode. This clock generator is also the source of the master clock output. Two
additional registers are available in I
configuration SPI_I2SPR and the other one is a generic I
SPI_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock
polarity, etc.).
The SPI_CR1 register and all CRC registers are not used in the I
SSOE bit in the SPI_CR2 register and the MODF and CRCERR bits in the SPI_SR are not
used.
2
The I S uses the same SPI register for data transfer (SPI_DR) in 16-bit wide mode.
25.4.2

Supported audio protocols

The three-line bus has to handle only audio data generally time-multiplexed on two
channels: the right channel and the left channel. However there is only one 16-bit register
for the transmission and the reception. So, it is up to the software to write into the data
register the adequate value corresponding to the considered channel side, or to read the
data from the data register and to identify the corresponding channel by checking the
CHSIDE bit in the SPI_SR register. Channel Left is always sent first followed by the channel
right (CHSIDE has no meaning for the PCM protocol).
Four data and packet frames are available. Data may be sent with a format of:
•
16-bit data packed in 16-bit frame
•
16-bit data packed in 32-bit frame
•
24-bit data packed in 32-bit frame
•
32-bit data packed in 32-bit frame
When using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant
bits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only
one read/write operation).
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2
S interface when the I
2
S mode. One is linked to the clock generator
DocID13902 Rev 15
2
S capability is enabled (by
2
S is configured in master
2
S configuration register
2
S mode. Likewise, the
RM0008
, where
S