Low-, Medium-, High- And Xl-Density Reset And Clock Control (Rcc); Reset; System Reset - ST STM32F101 series Reference Manual

RM0008
7 Low-, medium-, high- and XL-density reset and clock
control (RCC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This Section applies to low-, medium-, high- and XL-density STM32F10xxx devices.
Connectivity line devices are discussed in a separate section (refer to
devices: reset and clock control (RCC) on page
7.1

Reset

There are three types of reset, defined as system reset, power reset and backup domain
reset.
7.1.1

System reset

A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see
5. Low-power management reset (see
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see
Software reset
The SYSRESETREQ bit in Cortex
must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex
programming manual (see

Low-, medium-, high- and XL-density reset and clock control (RCC)

Section 7.3.10: Control/status register
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-M3 Application Interrupt and Reset Control Register
Related documents on page
DocID13902 Rev 15
123).
Software reset)
Low-power management
(RCC_CSR)).
1) for more details.
Connectivity line
Figure 4).
reset)
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-M3
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