RM0008
27.5
USART mode configuration
Asynchronous mode
Hardware Flow Control
Multibuffer Communication (DMA)
Multiprocessor Communication
Synchronous
Smartcard
Half-Duplex (Single-Wire mode)
IrDA
LIN
1. X = supported; NA = not applicable.
27.6
USART registers
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
Universal synchronous asynchronous receiver transmitter (USART)
Figure 301. USART interrupt mapping diagram
TC
TCIE
TXE
TXEIE
CTS
CTSIE
IDLE
IDLEIE
RXNEIE
ORE
RXNEIE
RXNE
PE
PEIE
LBD
LBDIE
FE
NE
EIE
ORE
DMAR
Table 199. USART mode configuration
USART modes
Section 2.1 on page 47
USART1
USART2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
for a list of abbreviations used in register descriptions.
DocID13902 Rev 15
interrupt
(1)
USART3
UART4
X
X
X
X
NA
NA
X
X
NA
X
X
X
X
NA
NA
X
NA
NA
X
X
X
X
X
X
X
X
X
USART
UART5
810/1128
820
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