ST STM32F101 series Reference Manual page 750

RM0008
SCL master clock generation
The CCR bits are used to generate the high and low level of the SCL clock, starting from the
generation of the rising and falling edge (respectively). As a slave may stretch the SCL line,
the peripheral checks the SCL input from the bus at the end of the time programmed in
TRISE bits after rising edge generation.
•
If the SCL line is low, it means that a slave is stretching the bus, and the high level
counter stops until the SCL line is detected high. This allows to guarantee the minimum
HIGH period of the SCL clock parameter.
•
If the SCL line is high, the high level counter keeps on counting.
Indeed, the feedback loop from the SCL rising edge generation by the peripheral to the SCL
rising edge detection by the peripheral takes time even if no slave stretches the clock. This
loopback duration is linked to the SCL rising time (impacting SCL VIH input detection), plus
delay due to the noise filter present on the SCL input path, plus delay due to internal SCL
input synchronization with APB clock. The maximum time used by the feedback loop is
programmed in the TRISE bits, so that the SCL frequency remains stable whatever the SCL
rising time.
Start condition
Setting the START bit causes the interface to generate a Start condition and to switch to
Master mode (MSL bit set) when the BUSY bit is cleared.
Note: In master mode, setting the START bit causes the interface to generate a ReStart condition
at the end of the current byte transfer.
Once the Start condition is sent:
•
The SB bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address (see
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
•
In 10-bit addressing mode, sending the header sequence causes the following event:
–
Then the master waits for a read of the SR1 register followed by a write in the DR
register with the second address byte (see
sequencing).
–
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see
•
In 7-bit addressing mode, one address byte is sent.
As soon as the address byte is sent,
–
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see
Figure 272
The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Figure 272 and
The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Figure 272 and
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Inter-integrated circuit (I
and Figure 273
Figure 272
Figure 273 Transfer sequencing).
Figure 273 Transfer sequencing).
Transfer sequencing EV5).
and Figure 273 Transfer
2
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