Clock Source - ST STM32F101 series Reference Manual

RM0008
Figure 176. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
Figure 177. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
17.3.3

Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 178
without prescaler.
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
Write a new value in TIMx_ARR
shows the behavior of the control circuit and the upcounter in normal mode,
DocID13902 Rev 15
preloaded)
31 32 33 34 35 36 00
FF
preloaded)
F0 F1 F2 F3 F4 F5 00
F5
F5
Basic timers (TIM6&TIM7)
01 02 03 04 05 06 07
36
01 02 03 04 05 06 07
36
36
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