Configuration Register (Wwdg_Cfr); Status Register (Wwdg_Sr) - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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Configuration register (WWDG_CFR)

Address offset: 0x04

Reset value: 0x0000 007F

Bit 31:10 Reserved, must be kept at reset value.

Bit 9 EWI: Early wakeup interrupt

Bits 8:7 WDGTB[1:0]: Timer base

Bits 6:0 W[6:0]: 7-bit window value

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EWIF: Early wakeup interrupt flag

When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is

only cleared by hardware after a reset.

The time base of the prescaler can be modified as follows:

00: CK Counter Clock (PCLK1 div 4096) div 1

01: CK Counter Clock (PCLK1 div 4096) div 2

10: CK Counter Clock (PCLK1 div 4096) div 4

11: CK Counter Clock (PCLK1 div 4096) div 8

These bits contain the window value to be compared to the downcounter.

This bit is set by hardware when the counter has reached the value 0x40. It must be cleared

by software by writing '0. A write of '1 has no effect. This bit is also set if the interrupt is not

DocID13902 Rev 15

Window watchdog (WWDG)