Wwdg Registers; Control Register (Wwdg_Cr) - ST STM32F101 series Reference Manual

Window watchdog (WWDG)
20.6

WWDG registers

Refer to
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
20.6.1

Control register (WWDG_CR)

Address offset: 0x00
Reset value: 0x0000 007F
31 30 29 28
15 14 13 12
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 WDGA: Activation bit
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
495/1128
Section 2.1 on page 47
27 26 25
11 10 9
Reserved
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
These bits contain the value of the watchdog counter. It is decremented every (4096 x
WDGTB
2 ) PCLK1 cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6
becomes cleared).
for a list of abbreviations used in register descriptions.
24 23 22
Reserved
8 7 6
WDGA
rs
DocID13902 Rev 15
21 20 19 18
5 4 3 2
T[6:0]
rw
RM0008
17 16
1 0