Tim6&Tim7 Status Register (Timx_Sr); Tim6&Tim7 Event Generation Register (Timx_Egr); Tim6&Tim7 Counter (Timx_Cnt) - ST STM32F101 series Reference Manual

RM0008
17.4.4 TIM6&TIM7 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15 14 13
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UIF: Update interrupt flag
– At overflow or underflow and if UDIS = 0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0
17.4.5 TIM6&TIM7 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15 14 13
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).
17.4.6 TIM6&TIM7 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CNT[15:0]: Counter value
12 11 10 9
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
and UDIS = 0 in the TIMx_CR1 register.
12 11 10 9
12 11 10 9
rw rw rw rw
8 7 6
Reserved
8 7 6
Reserved
8 7 6
CNT[15:0]
rw rw rw
DocID13902 Rev 15
Basic timers (TIM6&TIM7)
5 4 3 2
5 4 3 2
5 4 3 2
rw rw rw rw
1 0
UIF
rc_w0
1 0
UG
w
1 0
rw rw
470/1128
472