Memory And Bus Architecture; System Architecture; Figure 1. System Architecture (Low-, Medium-, Xl-Density Devices) - ST STM32F101 series Reference Manual

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Memory and bus architecture

3.1

System architecture

In low-, medium-, high- and XL-density devices, the main system consists of:
•
Four masters:
–
–
•
Four slaves:
–
–
–
–
These are interconnected using a multilayer AHB bus architecture as shown in
Cortex-M3
DMA1
Ch.1
Ch.2
Ch.7
DMA2
Ch.1
Ch.2
Ch.5
®
Cortex -M3 core DCode bus (D-bus) and System bus (S-bus)
GP-DMA1 & 2 (general-purpose DMA)
Internal SRAM
Internal Flash memory
FSMC
AHB to APBx (APB1 or APB2), which connect all the APB peripherals

Figure 1. System architecture (low-, medium-, XL-density devices)

ICode
DCode
Sys tem
DMA
DocID13902 Rev 15
FLITF
FSMC
SDIO
Bridge 2
AHB system bus
Bridge 1
Reset & clock
control (RCC)
DMA Request
DMA request
Memory and bus architecture
Figure
Flash
SRAM
APB 1
APB2
DAC SPI3/I2S
ADC1 GPIOC
ADC2 GPIOD PWR SPI2/I2S
ADC3
GPIOE BKP IWDG
USART1
GPIOF
bxCAN WWDG
SPI1
GPIOG
RTC
USB
TIM1
EXTI
I2C2 TIM7
TIM8 AFIO
I2C1 TIM6
GPIOA
UART5 TIM5
GPIOB
TIM4
UART4
TIM3
USART3
TIM2
USART2
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