Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr) - ST STM32F101 series Reference Manual

RM0008
Bit 4 FLITFEN: FLITF clock enable
Bit 3 Reserved, must be kept at reset value.
Bit 2 SRAMEN: SRAM interface clock enable
Bit 1 DMA2EN: DMA2 clock enable
Bit 0 DMA1EN: DMA1 clock enable
8.3.7

APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
31 30 29
15 14 13
SPI1
USART
1EN
Res. Res.
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Bits 31:15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI 1 clock enable
Set and cleared by software.
0: SPI 1 clock disabled
1: SPI 1 clock enabled
Set and cleared by software to disable/enable FLITF clock during sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode
1: SRAM interface clock enabled during Sleep mode
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
28 27 26 25
12 11 10 9
TIM1 ADC2 ADC1
EN EN EN EN
rw rw rw rw
Connectivity line devices: reset and clock control (RCC)
24 23 22
Reserved
8 7 6
IOPE
EN
Reserved
rw
DocID13902 Rev 15
21 20 19 18
5 4 3 2
IOPD IOPC IOPB IOPA
EN EN EN EN
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17 16
1 0
AFIO
EN
Res.
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