Adc Regular Sequence Register 2 (Adc_Sqr2) - ST STM32F101 series Reference Manual

Analog-to-digital converter (ADC)

11.12.10 ADC regular sequence register 2 (ADC_SQR2)

Address offset: 0x30
Reset value: 0x0000 0000
31 30 29 28
Reserved
rw rw
15 14 13 12
SQ10_
SQ9[4:0]
0
rw rw rw rw
Bits 31:30
Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence
These bits are written by software with the channel number (0..17) assigned as the 12th in the
sequence to be converted.
Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence
Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence
Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence
Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence
Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence
247/1128
27 26 25
SQ12[4:0]
rw rw rw
11 10 9
rw rw rw
Reserved, must be kept at reset value.
DocID13902 Rev 15
24 23 22 21
SQ11[4:0]
rw rw rw rw
8 7 6 5
SQ8[4:0]
rw rw rw rw
20 19 18 17
SQ10[4:1]
rw rw rw rw
4 3 2 1
SQ7[4:0]
rw rw rw rw
RM0008
16
rw
0
rw